With increasing data-rates in modern electronic designs, functional schematic simulations may need to account for layout parasitics to ensure accurate simulation results. Accounting for parasitics has become even more important for RF (radio frequency), analog, or mixed-signal electronic designs where layout parasitics may drastically impact electrical characteristics (e.g., voltages and currents) and hence the performance, reliability, manufacturability, and quality of the electronic deigns. Parasitics may come from IC-layout and/or package-layout and affect the performance, reliability, manufacturability, and quality of the electronic design. Traditional approaches use extraction techniques to extract IC (integrated circuit)-layout parasitics as RC (resistance, capacitance) values. The extracted parasitics are often not sufficiently accurate for electronic designs where package-layout geometries are two-and-a-half-dimensional or three-dimensional in nature and may thus be inductive, especially with complex coupling with their neighboring components
As a result, IC bumps, package balls, vias, and/or dense routing over large package geometries may need to be extracted as complex macro-models. When such macro-models representing the parasitics are inserted into schematics for “parasitic aware circuit simulations”, the schematic may become overly complicated as connections are abutted to join various sources and destinations and models are inserted. Conventional approaches thus require a manual process for such macro-model insertion, and with such conventional approaches the schematic may start to lose its readability and may not be able to drive PCB (printed circuit board)/package implementation.
In addition, conventional approaches may not account for complex models such as s-parameter models, SPICE (simulation program with integrated circuit emphasis) sub-circuit models, or IBIS (input output buffer information specification) models that often include multiple coupled nets. Furthermore, a user may need to quickly perform multiple what-if analyses to examine the impact of changing parasitics on the electronic design. With conventional approaches, users simply cannot selectively probe the inserted complex models, not to mention performing any quick evaluation or analyses (e.g., what-if analysis analyses) where multiple simulations with different model associations need to be performed. Conventional approaches may also fail when a net to be extracted is common or shared across two models. Some conventional approaches are further limited to parasitic stitching and cannot handle model annotation for instances of various circuit design components or blocks. Conventional approach also cannot change model associations unless the cell view of an inserted symbol is modified for the name of the sub-circuit of interest.
Therefore, there exists a need to back annotate and visualize parasitic models for electronic designs without any of the aforementioned issues or limitations.